1. Field of the Invention
The embodiments of the invention generally relate to noise reduction, and, more particularly, to methods for synthesis of low-noise pipelined designs.
2. Description of the Related Art
Chips manufactured today are getting larger and continue to demand increased performance of the system. The increase in chip size is driven by the need to integrate an entire system-on-chip (SoC). SoC design minimizes chip-to-chip communication and thus generally improves overall performance. Such integrated designs place noise-producing digital circuits next to noise-sensitive analog circuits and introduce new challenges of designing low-noise digital circuits and noise-immune analog circuits.
A large contributor to the overall chip noise is the clock signaling of latches, and the subsequent signal propagation in the logic that follows each latch. Typically all latches are clocked at the same time. The current demand from the supply spikes at the beginning of each clock signal cycle introducing the highest supply and substrate noise. The noise problem is compounded by aggressively pipelined designs, which not only increase the signal frequency, but also the number of latches that need to be clocked.
In pipelined designs, these latches are placed at equal intervals, bounding maximum combinational logic that could be traversed by a propagating signal during a single clock signal cycle. Pipelined designs divide the critical path of a specific design into smaller clocking domains and smaller clock signal allocations across the chip. This approach maintains equal propagation delays in all stages of the pipeline but also concentrates most of the clocking current demand at one clock signal edge. A method for spreading the current demand over the entire clock signal cycle would significantly improve the peak noise levels on chip.
U.S. Pat. No. 6,463,005 B2, incorporated herein by reference, teaches the method of noise reduction by staggering the switching of the (largely capacitive) column lines in an (memory) array. U.S. Pat. No. 5,646,543, incorporated herein by reference, reduces inductive noise by staggering the activation of off-chip drivers. U.S. Pat. No. 6,711,724, incorporated herein by reference, teaches pipeline based circuits with a clock signaling mechanism.